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NXP Semiconductors /QN908XC /CS /LP_CTRL

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Interpret as LP_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DEBONCE_NUM 0 (DISABLE)LP_EN 0LP_CH0THR

LP_EN=DISABLE

Description

Control register for low power mode

Fields

DEBONCE_NUM

(DEBONCE_NUM+1) consecutive samples to judge one touch action.
LP_EN

Enable for low power mode.

0 (DISABLE): Low power mode disable.

1 (ENABLE): Low power mode enable.
LP_CH

The index of the channel to monitor in low power mode, representing 0~7.
THR

Threshold to decide the touch action.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data